In the fabrication of integrated circuits (IC), individual semiconductor devices and electronic elements formed within the semiconductor substrate must in turn be connected with one or more metallization levels. These metallization levels form the desired inter-connections between the individual electronic elements and also the connections to outside leads. Typically, an individual electronic element is coupled to a metallization level via a stud or contact which extends through a passivation layer and physically contacts both the metallization level and the electronic element.
However, due to extremely high device densities incorporated within many of today's integrated circuits the method of forming the metallization contacts must be compatible with an ever increasing variety of structures and devices. For example, many CMOS structures often employ borderless diffusion regions adjacent isolation regions. These isolation regions commonly employ a shallow trench insulation (STI) structure which may be filled with a dielectric material such as silicon oxide. With such a structure the goal of metallization contact (MC) etching is to uniformly expose the contact area of the diffusion regions while etching a minimum of the STI fill. Although fill erosion may be reduced by increasing the etch selectivity between the passivation layer and an etch stop, it is still necessary for the process to utilize an over-etch in order to guarantee opening of all MC to diffusion contact areas. Thus, this etching process commonly causes erosion of the STI fill and exposure of a lightly doped region of the semiconductor substrate within the diffusion. Moreover, it should be noted that in addition to MC etching, other steps such as pad and sacrificial oxide strips, spacer etching, salicide pre-cleans and other processes also contribute to fill pulldown and exposure of lightly doped regions of electronic elements.
Exposure of the lightly doped semiconductor substrate of electronic elements, such as diffusions, is undesirable since electrical coupling of the same with the metallization contact often causes "leaky" contacts. In this regard the dopant concentration of the semiconductor substrate affects the work function of the semiconductor material and it is the work function of this material in relation to the work function of the material comprising the metallization contact that will determine the contact properties. Typically, coupling of a highly doped semiconductor material with a low resistance contact, such as a metal, results in good low-leakage contacts. However, coupling of a lightly doped semiconductor substrate and a metal often results in a poor contact and is, therefore, undesirable.
Similarly caused leakage problems in other integrated circuits have been avoided by having deeper junctions. However, due to the large variety of IC designs and their corresponding device densities, utilization of deeper junctions is often not an option. For example, a deep junction immediately adjacent to a gate may often create adverse affects on FET device behavior. Devices utilizing a thin gate electrode (e.g. 200 nM) often experience local threshold fluctuations when higher energy implants are channeled through the thin polysilicon layer in order to form the deeper junctions. Alternatively, using a faster diffusing species for achieving greater junction depth is similarly limited since implants do not diffuse in a completely vertical fashion and junctions of an opposite donor type are commonly adjacent these junctions. Thus long diffusions are often insupportable, particularly in high density devices.
Utilization of oxide or nitride spacers inside the metallization contact holes has been suggested. However, preliminary attempts at employing such a strategy has meet with poor success since shallow trench isolation corners are not repeatedly and sufficiently vertical and anisotropy of etches is degraded in small crevices. Another attempted solution is adding appropriately masked implants after contact hole etching, where appropriate dopant species are implanted into unfilled empty holes. However, activation of the dopants within salicided diffusions and other electronic elements then becomes difficult since the implant energies needed to effect such implants must be substantial and the ions must penetrate vertically through the silicon at least as far as the maximum pulldown depths.
Therefore, there exists a need for semiconductor devices and a process for making the same which provide low-leakage borderless contacts between metallization levels and doped electronic elements. There further exists a need for such a process that utilizes techniques compatible with a wide variety of pre-existing electronic elements and semiconductor structures. Further, there exits a need for such a process which does not utilize techniques or incorporate structures which will significantly increase either the surface area or height occupied by the device.